CPU 9980xe support.

This issue has been created since 2019-09-30.

I have a 9980xe and a 6850k that don't show the voltages on all cpus.
I saw another issue thread where some code changes were made to support.
What should I change to support these cpus?

Also, is there any way to make the corefreq cli run multi-instance?

TDP-9000w wrote this answer on 2019-09-30
./corefreq-cli -s -m
Processor                            [Intel(R) Core(TM) i9-9980XE CPU @ 3.00GHz]
|- Architecture                                                      [Skylake/X]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [  33554526]
|- Signature                                                           [  06_55]
|- Stepping                                                            [      4]
|- Online CPU                                                          [ 18/ 18]
|- Base Clock                                                          [ 99.997]
|- Frequency            (MHz)                      Ratio                        
                 Min   1199.97                    [  12 ]                       
                 Max   2999.92                    [  30 ]                       
|- Factory                                                             [100.000]
                       3000                       [  30 ]                       
|- Performance                                                                  
   |- OSPM                                                                      
                 TGT   4199.89                    <  42 >                       
|- Turbo Boost                                                         [ UNLOCK]
                  1C   4199.89                    <  42 >                       
                  2C   4199.89                    <  42 >                       
                  3C   4199.89                    <  42 >                       
                  4C   4199.89                    <  42 >                       
                  5C   4199.89                    <  42 >                       
                  6C   4199.89                    <  42 >                       
                  7C   4199.89                    <  42 >                       
                  8C   4199.89                    <  42 >                       
                  9C    199.99                    <   2 >                       
                 10C    399.99                    <   4 >                       
                 11C    799.98                    <   8 >                       
                 12C   1199.97                    <  12 >                       
                 13C   1599.96                    <  16 >                       
                 14C   1799.95                    <  18 >                       
                 15C   2399.94                    <  24 >                       
                 16C   2799.93                    <  28 >                       
|- Uncore                                                              [ UNLOCK]
                 Min   2699.93                    <  27 >                       
                 Max   2699.93                    <  27 >                       
|- TDP                                                           Level [  0:2  ]
   |- Programmable                                                     [ UNLOCK]
   |- Configuration                                                    [   LOCK]
   |- Turbo Activation                                                 [ UNLOCK]
             Nominal   2999.92                    [  30 ]                       
              Level1   2099.94                    [  21 ]                       
              Level2   2099.94                    [  21 ]                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX-512      [Y]  BMI1/BMI2 [Y/Y]      CLFLUSH [Y]        CMOV [Y] 
|- CMPXCHG8B    [Y]   CMPXCHG16B [Y]         F16C [Y]         FPU [Y] 
|- FXSR         [Y]    LAHF/SAHF [Y]    MMX/Ext [Y/N]  MONITOR/X[Y/N] 
|- MOVBE        [Y]          MPX [Y]    PCLMULQDQ [Y]      POPCNT [Y] 
|- RDRAND       [Y]       RDSEED [Y]       RDTSCP [Y]         SEP [Y] 
|- SGX          [N]          SSE [Y]         SSE2 [Y]        SSE3 [Y] 
|- SSSE3        [Y]  SSE4.1/4A [Y/N]       SSE4.2 [Y]     SYSCALL [Y] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Present]
|- Advanced Configuration & Power Interface                     ACPI   [Present]
|- Advanced Programmable Interrupt Controller                   APIC   [Present]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Present]
|- Debugging Extension                                            DE   [Present]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Present]
|- CPL Qualified Debug Store                                  DS-CPL   [Present]
|- 64-Bit Debug Store                                         DTES64   [Present]
|- Fast-String Operation                                Fast-Strings   [Present]
|- Fused Multiply Add                                       FMA|FMA4   [Present]
|- Hardware Lock Elision                                         HLE   [Present]
|- Long Mode 64 bits                                         IA64|LM   [Present]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Present]
|- Model Specific Registers                                      MSR   [Present]
|- Memory Type Range Registers                                  MTRR   [Present]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Present]
|- Physical Address Extension                                    PAE   [Present]
|- Page Attribute Table                                          PAT   [Present]
|- Pending Break Enable                                          PBE   [Present]
|- Process Context Identifiers                                  PCID   [Present]
|- Perfmon and Debug Capability                                 PDCM   [Present]
|- Page Global Enable                                            PGE   [Present]
|- Page Size Extension                                           PSE   [Present]
|- 36-bit Page Size Extension                                  PSE36   [Present]
|- Processor Serial Number                                       PSN   [Missing]
|- Restricted Transactional Memory                               RTM   [Present]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Present]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Present]
|- Virtual Mode Extension                                        VME   [Present]
|- Virtual Machine Extensions                                    VMX   [Present]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- Execution Disable Bit Support                              XD-Bit   [Present]
|- XSAVE/XSTOR States                                          XSAVE   [Present]
|- xTPR Update Control                                          xTPR   [Present]
                                                                                
Technologies                                                                    
|- System Management Mode                                   SMM-Dual       [ ON]
|- Hyper-Threading                                               HTT       [OFF]
|- SpeedStep                                                    EIST       < ON>
|- Dynamic Acceleration                                          IDA       [ ON]
|- Turbo Boost                                                 TURBO       < ON>
|- Virtualization                                                VMX       [OFF]
   |- I/O MMU                                                   VT-d       [OFF]
   |- Hypervisor                                                           [OFF]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  4]
|- Counters:          General                   Fixed                           
|                     8 x 48 bits             3 x 48 bits                       
|- Enhanced Halt State                                           C1E       <OFF>
|- C1 Auto Demotion                                              C1A       <OFF>
|- C3 Auto Demotion                                              C3A       <OFF>
|- C1 UnDemotion                                                 C1U       <OFF>
|- C3 UnDemotion                                                 C3U       <OFF>
|- Frequency ID control                                          FID       [OFF]
|- Voltage ID control                                            VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware-Controlled Performance States                        HWP       [OFF]
|- Hardware Duty Cycling                                         HDC       [OFF]
|- Package C-State                                                              
   |- Configuration Control                                   CONFIG   [   LOCK]
   |- Lowest C-State                                           LIMIT   [      0]
   |- I/O MWAIT Redirection                                  IOMWAIT   [ Enable]
   |- Max C-State Inclusion                                    RANGE   [      3]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     0     2     0     0     0     0              
|- Core Cycles                                                         [Present]
|- Instructions Retired                                                [Present]
|- Reference Cycles                                                    [Present]
|- Last Level Cache References                                         [Present]
|- Last Level Cache Misses                                             [Present]
|- Branch Instructions Retired                                         [Present]
|- Branch Mispredicts Retired                                          [Present]
                                                                                
Power & Thermal                                                                 
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   <      6>
   |- Energy Policy                                          HWP EPP   [      0]
|- Junction Temperature                                        TjMax   [  0:110]
|- Digital Thermal Sensor                                        DTS   [Present]
|- Power Limit Notification                                      PLN   [Present]
|- Package Thermal Management                                    PTM   [Present]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Present]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000061035]
   |- Window                                            second   [  0.000976562]
CPU Pkg  Apic  Core Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID    ID     ID  L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP     0     0      0   32768  8     32768  8   1048576 16  25952256 11  
001:  0     2     1      0   32768  8     32768  8   1048576 16  25952256 11  
002:  0     4     2      0   32768  8     32768  8   1048576 16  25952256 11  
003:  0     6     3      0   32768  8     32768  8   1048576 16  25952256 11  
004:  0     8     4      0   32768  8     32768  8   1048576 16  25952256 11  
005:  0    16     8      0   32768  8     32768  8   1048576 16  25952256 11  
006:  0    18     9      0   32768  8     32768  8   1048576 16  25952256 11  
007:  0    20    10      0   32768  8     32768  8   1048576 16  25952256 11  
008:  0    22    11      0   32768  8     32768  8   1048576 16  25952256 11  
009:  0    32    16      0   32768  8     32768  8   1048576 16  25952256 11  
010:  0    34    17      0   32768  8     32768  8   1048576 16  25952256 11  
011:  0    36    18      0   32768  8     32768  8   1048576 16  25952256 11  
012:  0    38    19      0   32768  8     32768  8   1048576 16  25952256 11  
013:  0    40    20      0   32768  8     32768  8   1048576 16  25952256 11  
014:  0    48    24      0   32768  8     32768  8   1048576 16  25952256 11  
015:  0    50    25      0   32768  8     32768  8   1048576 16  25952256 11  
016:  0    52    26      0   32768  8     32768  8   1048576 16  25952256 11  
017:  0    54    27      0   32768  8     32768  8   1048576 16  25952256 11 
TDP-9000w wrote this answer on 2019-09-30

Full load with Prime95
4 to 4.2ghz Stable vcore 1.135 (bios) (bios pics to follow)
Cooked, 177degF NH-D15S air cooled. (ugh) oclock with this cooler and cpu is not gunna happen.

4-4 2ghz

4-4 2ghz

Dashboard shows 0? for some things....
4ghz dashboard

BIOS
CpuClockBIOS

CpuPowerManagement

PlatformMisc

MiscINFO

cyring wrote this answer on 2019-10-01

Nice processor!

  • For all CPU voltage, move this switch case...

case VOLTAGE_FORMULA_INTEL_SKL_X:

... just bellow...

case VOLTAGE_FORMULA_INTEL:

  • About multi-client support : it will impact Daemon. What's your use case?

  • Skylake/X Uncore is not fully implemented b/c lack of hardware to work/test with. Same for IMC.

  • Screenshots, I see wrong power measurements of 4W full Cores stressed. To debug

TDP-9000w wrote this answer on 2019-10-01

What's your use case?
Just local use...
I just want to run the regular corefreq-cli command in one terminal
ALONG with a corefreq-cli -V in another terminal window.
When I do both, one of them stops.
Yea hardware should be cheaper! Luck has it that I have access to this!
I can test stuff/screenshot/debug if you want to code more for this platform.
It already looks AWESOME.. The work you already did makes this program very useful!
Thanks, i will give the voltage fix a try.
I'll make a new thread for the 6850k cpu.

TDP-9000w wrote this answer on 2019-10-01

Good, thank you. It now shows the voltages on all cores... since i have all cores vlocked right now, they are the same.
9980xe-1 135v4 1ghz

Now I need to change the vcore to auto and watch the clocks, voltages, etc and write them down to get an idea of what each core can do at full use under heat. Some cores like to run 4.7ghz, and others hate it.

cyring wrote this answer on 2019-10-01
  • Fix released in latest version 1.66.5

  • About 4.7 GHz, try one of my stress tools: go to [F2] Menu > Tools or shortcut [O]
    Conics variants involve the FPU; others stress the ALU
    Press [F10] at any time to stop stressing loops.

cyring wrote this answer on 2019-10-01

Not sure if it is the right product sheet, but I'm noticing some gaps:

  • CoreFreq got a TjMax of 110 whereas spec says 84°C
    Please check if temperature in Celsius is right ?
  • Turbo Boost or Turbo Max is version 3.
    In the Cli, do you read this version number beside TURBO in the "Technologies" window ?

I've noticed C-States are disabled in your BIOS. Could you activate them and check that they are well measured by CoreFreq

  1. Core C-States
  2. Package C-States

Also can you enable in BIOS and verify the state of SpeedStep, HyperThreading and VT is well reported

About Power, this needs some debug code but we need a reference : not sure about a max of 165W

cyring wrote this answer on 2019-10-01
  • On-Demand Clock Modulation
    Could you check if this legacy feature works with Skylake/X
  1. Activate the Experimental Mode in Settings
    2019-10-01-160539_644x316_scrot
  2. Enable Clock Modulation
    2019-10-01-160553_644x316_scrot
  3. Once ODCM enabled, change the DutyCycle to 25%
    2019-10-01-160616_644x316_scrot
  4. Starts a stress Tool on a selected CPU and check if the Core frequency is limited to 25% of its max
    2019-10-01-160724_644x316_scrot
  5. Restore the CPU nominal frequency by deactivating Clock Modulation. Frequency should go back to its top value.
    2019-10-01-160754_644x316_scrot
  • Remarks:
  1. Clock Modulation is an untested feature with SKL/X, please save, sync your files before testing
  2. If test is OK, I will remove the Experimental requirement for SKL/X in next CoreFreq release

Thank you

cyring wrote this answer on 2019-10-01

Some cores like to run 4.7ghz, and others hate it.

In datasheet vol 1

  1. Turbo Boost Max 3.0, one of the Core should be set in BIOS to realize the highest performance.
    This CPU is the one to stress in the Tools > Turbo Select CPU...
  2. With my Nehalem, Turbo Boost works only with SpeedStep enabled.
    The Technologies window can let you enable them at any time.
  3. Overclock the One Core Ratio in Turbo Boost section, item 1C
    2019-10-01-223219_644x420_scrot

$ 5.2.5: The Target Ratio has to be set to the max value.

  1. set the Bias Hint to the lowest energy policy in Power & Thermal window
    2019-10-01-224202_644x420_scrot

  2. in Processor window, the OSPM TGT can be set to a fixed ratio.
    This requires however to let CoreFreq driver be registered as the OS CPU-Freq driver (thus blacklist any other drivers)
    2019-10-01-223037_644x420_scrot

  • In your previous output, HWP appears OFF.
    Not sure if the BIOS can present this feature. If feasible then:
  1. enable HWP in Performance window
  2. set HWP-EPP to the lowest energy profile in Power & Thermal window
  3. set the HWP TGT Target and HWP Max Ratio to the highest value in Processor window.
  • If the CoreFreq kernel module is registered as the OS Idle driver then you can set one idle limit in the Kernel data window to reduce the C-State latency to C1 during the CPU stress.
    2019-10-01-222543_644x420_scrot
cyring wrote this answer on 2019-10-01

Edit: That's the only Datasheet volume 2 relative to X-Series I found.
Table 2-3 mentions an HOST and DRAM Controller Device ID of 906E9 .
But it looks like a typo error, it can't be 5 hexa digits.

Can you check|print the output of lspci -nn

May be the IMC ID is already defined but not associated with the SKL/X architecture yet.

/* Source: 6th Generation Intel® Processor Datasheet for S-Platforms Vol2 */

If found among the Skylake IDs then the list can be changed at this line:
.PCI_ids = PCI_Skylake_X_ids,

with

	.PCI_ids = PCI_Skylake_ids,

Next, rebuild and check if the Cli shows the Memory Controller data

TDP-9000w wrote this answer on 2019-10-01

Ok, lots of stuff to try.

The datasheets you linked are not? the correct ones.

I found two datasheets here.
https://www.intel.com/content/www/us/en/products/processors/core/x-series/i9-9980xe.html#relatedresourcesblad

9980XE datasheet.
https://www.intel.com/content/www/us/en/products/processors/core/6th-gen-x-series-datasheet-vol-1.html

Spec update.
https://www.intel.com/content/www/us/en/products/docs/processors/core/6th-gen-x-series-spec-update.html

The vol1 datasheet implies theres a vol2. but i can't find it.

All "memory" related output:

$ lspci -nn
Memory controller [0580]: Intel Corporation 200 Series/Z370 Chipset Family Power Management Controller [8086:a2a1]

System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2066] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2066] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2040] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2041] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2042] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2043] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2044] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LM Channel 1 [8086:2045] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LMS Channel 1 [8086:2046] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LMDP Channel 1 [8086:2047] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E DECS Channel 2 [8086:2048] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LM Channel 2 [8086:2049] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LMS Channel 2 [8086:204a] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LMDP Channel 2 [8086:204b] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2040] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2041] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2042] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2043] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E Integrated Memory Controller [8086:2044] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LM Channel 1 [8086:2045] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LMS Channel 1 [8086:2046] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LMDP Channel 1 [8086:2047] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E DECS Channel 2 [8086:2048] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LM Channel 2 [8086:2049] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LMS Channel 2 [8086:204a] (rev 04)
System peripheral [0880]: Intel Corporation Sky Lake-E LMDP Channel 2 [8086:204b] (rev 04)
TDP-9000w wrote this answer on 2019-10-01

So, Running two instances of corefreq-cli would allow me to monitor all 3 things at once,
core voltages, core temperatures, and core frequency.
Switching the window to see the voltages causes a delay, so screenshots of all 3 are not possible for analysis.

Or.... It would be useful for the voltage page to show core temps also.
Fail-Pass
Fail-Pass1

Does your stress tools verify errors and stop only the core that failed?
I use prime95 because it only stops the core that fails the test, but keeps others going.
This allows one to determine the weakest cores versus the strongest in relation to initial thermal stress package hot spots.

It also helps to determine your platform thermal capabilities, mine, air cooled cpu, the NH-D15S with max fan speed says I can run about 5 specific cores at 4.2 ghz. without going over the max temp.
Everyone says this chip is hot, and, it is. But its strong suit isn't heat, its the sheer number of raw cores, the soldered thermal interface allowing much greater watercooling and air thermal extraction provided you move enough air or water. I don't move enough air, and watercooling is a PITA, but perhaps one day when this chip gets aged...

cyring wrote this answer on 2019-10-02

So, Running two instances of corefreq-cli would allow me to monitor all 3 things at once,
core voltages, core temperatures, and core frequency.
Switching the window to see the voltages causes a delay, so screenshots of all 3 are not possible for analysis.

Or.... It would be useful for the voltage page to show core temps also.

This is definitively an enhancement to add. In addition to Energy/Power counters per Core for capable Processors such as Zen. Planed for next days ...

Does your stress tools verify errors and stop only the core that failed?
I use prime95 because it only stops the core that fails the test, but keeps others going.
This allows one to determine the weakest cores versus the strongest in relation to initial thermal stress package hot spots.

Nop, but it's a good use case to add.
So far, CoreFreq can claim the OS to disable a Core : press shortcut [#] then select CPU
2019-10-02-100049_644x316_scrot

TDP-9000w wrote this answer on 2019-10-02

So I think my memory controller is NOT in the coretypes.h you mentioned...
I saw numbers similar, but not exact.

Controller Device ID of : 0580 or 0880 or 8086,
I don't know which one, WTF is with intel and their datasheet not mentioning it.../ missing vol 2?
Not something we expect from such a company...
Whats next, intel cpus inside our crackerjack boxes?

I would just add it to the list somewhere formatting the entry like the others, but I do not know if that is all that is needed, nor do I know which ID should be used from the output of lspci above, I hope i included the proper info from that output.

cyring wrote this answer on 2019-10-02
  1. Location where you will store IDs for probing
    static struct pci_device_id PCI_Skylake_X_ids[] = {
  • This list contains device id to probe and the associated function which query registers
static struct pci_device_id PCI_Skylake_X_ids[] = {
	{
	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1234),
		.driver_data = (kernel_ulong_t) SKL_IMC
	},
	{0, }
};
  • you just have to copy the template above instead of the current empty list but replace 0x1234 with the IMC id. Datasheet mentions it as HA or SA Agent
    I would start with 0x2066 from your lspci output
  • list must be terminated by {0, }
  1. Rebuild and load the driver
  • if lucky SKL_IMC function may decode bits
    if your IMC platform works the same as Skylake/Desktop
  • High chance of CPU crash, save your files.
    even if no crash happens, check your kernel log for any error trapped
cyring wrote this answer on 2019-10-02
  1. Next add a case switch in the Daemon bellow this statement
    case PCI_DEVICE_ID_INTEL_SKYLAKE_DT_IMC_HA: /* Skylake/DT Server */
	case 0x1234:	/* Skylake/X */
		SKL_CAP(Shm, Proc, Core);
		SKL_IMC(Shm, Proc);
		SET_CHIPSET(IC_SUNRISEPOINT);
		break;
  • replace 0x1234 with the working IMC id you found
  • rebuild again, start Daemon then Client to read the IMC data
  • if Client does not allow the Memory Controller menu, it means no data has been correctly decoded.
TDP-9000w wrote this answer on 2019-10-02

I tried 0x2066 for both.
The daemon, and cli both start, but the client does nothing when selecting the memory controller menu. No errors under syslog, just statement of
kernel: corefreq: unload
kernel: corefreq: (6:-1): Processor [ 06_55] Architecture [Skylake/X] CPU [18/18]
But the DASHBOARD shows a BUS 8000MT if that means anything other than a label. If its read from the memory chip, something works?

image

0xa2a1, 0x2040 also shows the bus 8000MT.
I also tired 0x0580, 0x0880, and 0x8086 and those had all zeros for the bus.
So i think you have something at 0x2066, perhaps some data is correctly decoded, due to 8000MT being the actual number associated with this chip memory bandwidth, or its coincidental data.

cyring wrote this answer on 2019-10-02

Thank you for trying.
It means that all IDs tested have been probed, execution had followed the expected code path where bus speed is hard corded. Unfortunately registers failed to be queried. So we need find a specification of the architecture to decode the right registers. Especially the MCHBAR and the relative offsets where to query the IMC registers, plus the layout of their bits.

cyring wrote this answer on 2019-10-02

Does lspci give an ID facing BDF 0:0:0 ?

TDP-9000w wrote this answer on 2019-10-03

You mean this ?

lspci
Host bridge [0600]: Intel Corporation Sky Lake-E DMI3 Registers [8086:2020] (rev 04)
cyring wrote this answer on 2019-10-03

That's enough IDs and I bet this edac driver is running in your system ?
Enabling the kernel debug level should reveal its edac_dbg traces, and let us read the IMC properties.
Clearly this driver code shows registers and decoding protocol I never work with; and I wonder where those specs are coming from...

TDP-9000w wrote this answer on 2019-10-03

I tried turning on kernel debug but was confused at what string i should use.
Too many options...

        acpi.debug_layer=       [HW,ACPI,ACPI_DEBUG]
        acpi.debug_level=       [HW,ACPI,ACPI_DEBUG]
                        Format: <int>
                        CONFIG_ACPI_DEBUG must be enabled to produce any ACPI
                        debug output.  Bits in debug_layer correspond to a
                        _COMPONENT in an ACPI source file, e.g.,
                            #define _COMPONENT ACPI_PCI_COMPONENT
                        Bits in debug_level correspond to a level in
                        ACPI_DEBUG_PRINT statements, e.g.,
                            ACPI_DEBUG_PRINT((ACPI_DB_INFO, ...
                        The debug_level mask defaults to "info".  See
                        Documentation/acpi/debug.txt for more information about
                        debug layers and levels.

                        Enable processor driver info messages:
                            acpi.debug_layer=0x20000000
                        Enable PCI/PCI interrupt routing info messages:
                            acpi.debug_layer=0x400000
                        Enable AML "Debug" output, i.e., stores to the Debug
                        object while interpreting AML:
                            acpi.debug_layer=0xffffffff acpi.debug_level=0x2
                        Enable all messages related to ACPI hardware:
                            acpi.debug_layer=0x2 acpi.debug_level=0xffffffff

                        Some values produce so much output that the system is
                        unusable.  The "log_buf_len" parameter may be useful
                        if you need to capture more output.

https://www.kernel.org/doc/html/v4.14/admin-guide/kernel-parameters.html

I'll give these a try.

                        Enable all messages related to ACPI hardware:
                            acpi.debug_layer=0x2 acpi.debug_level=0xffffffff

                        Some values produce so much output that the system is
                        unusable.  The "log_buf_len" parameter may be useful
                        if you need to capture more output.

I'll use additional kernel start-up parameters of
log_buf_len=4M acpi.debug_layer=0x2 acpi.debug_level=0xffffffff
Unless you have a better parameter that gets the info needed better?
Also what info am i looking for, (in the syslog right?)

cyring wrote this answer on 2019-10-04

skx_edac is the driver to track.
Do a lsmod first to check if it is indeed running or not in your system.
If not, this driver never probes your Processor because not compatible with. (but maybe another edac_xxx may be listed)

In its source code, the edac_dbg prints are source of interest, such as DIMM geometry
https://elixir.bootlin.com/linux/latest/source/drivers/edac/skx_base.c#L526

In code, most traces seem at debug level 2; you can change level just for the time of restarting this driver, to find them among the last lines of kernel log.

modprobe -r skx_edac ; modprobe skx_edac
TDP-9000w wrote this answer on 2019-10-04

My lsmod lists nothing about edac. I loaded the result into a notepad searched it for edac, nothing.

cyring wrote this answer on 2019-10-12

Hello,

Version 1.67, per Core Temperature and RAPL counters added to the view Power & Voltage

Thanks for your tests

Regards

TDP-9000w wrote this answer on 2019-10-18

Ok, will get to those tests asap, thanks for the change works great.

So it turns out my logs show this:

EDAC skx: ECC is disabled on imc 0

So it must be there, but yet the lsmod output shows nothing edac.

cyring wrote this answer on 2019-10-18

Thanks.

So one EDAC static driver may run, not a module. I believe, the log can be dynamically increased to get further details.

I'm still refactoring the Voltage output which is now a 2^3 dimension (Voltage, Temp, Power), each matrix cell of 4 case values (None, Per SMT, Per Core, Per Package). Maths and code optimizations are still in progress.
I've released the intermediate version 1.67.4 which should conditionally display or not the relevant information depending on hardware. Feel free to post your View to let me evaluate any issues.

cyring wrote this answer on 2019-10-19

Refactoring of the view is completed in the latest version. Thank you for your returns.

More Details About Repo
Owner Name cyring
Repo Name CoreFreq
Full Name cyring/CoreFreq
Language C
Created Date 2015-06-21
Updated Date 2022-09-27
Star Count 1252
Watcher Count 52
Fork Count 96
Issue Count 4

YOU MAY BE INTERESTED

Issue Title Created Date Comment Count Updated Date
Enable Github Sponsors 1 2022-05-12 2022-09-18
Fix error while login 6 2021-12-06 2022-08-22
Relion4: Class3D - weird particle class assignment behaviour when skipping alignment 22 2021-10-20 2022-09-06
load_reusable_blocks() 0 2022-04-17 2022-08-22
There is a big difference between PE,SR and DV,RV. Why? 2 2022-08-24 2022-09-10
Feature request 0.0.0.0 1 2021-02-03 2022-09-01
Feature request for serve command 1 2021-02-10 2022-09-02
Deprecation warning: CLI options definitions were upgraded with "type" property 0 2021-04-12 2022-09-05
serverless framework deprecation warning: cli options definitions 1 2021-05-10 2022-08-29
AWS API Gateway Stage Variables Access 1 2021-05-05 2022-09-04
Use Google Calendar (iCal) as program source 3 2015-08-29 2022-07-28
Execution in CPU-only Mode 3 2021-07-03 2022-08-19
Specifying custom prefix tokens 3 2021-03-12 2022-08-31
[shine-cf] Portal service and portal service plan are not available anymore 1 2020-05-01 2022-09-20
몇몇 트위터 계정에서 읽어들이는 시간이 오래 걸립니다 3 2021-12-11 2022-09-13
Allow dropdown to be rendered as uncollapsed 1 2022-04-19 2022-08-07
RUSTSEC-2020-0056: stdweb is unmaintained 0 2022-05-21 2022-09-05
【Discuss】关于table的筛选图标,是不是靠左对齐比较好 4 2021-11-18 2022-09-16
ReferenceError: webpackChunkbuild is not defined 7 2021-07-13 2022-08-31
Low-priv article workflow: save not permitted after duplicate 5 2021-03-28 2022-09-12
Server down 1 2022-01-17 2022-01-12
Reverse proxy with nginx and qbittorrent-nox seems don't work 3 2022-05-30 2022-09-01
Keeps redirecting to login page 3 2021-11-19 2022-09-16
Grafana dashboard not generates metrics to Burning rate 2 2022-04-08 2022-09-27
PL qml.state() not supported on a simulator 2 2021-09-21 2022-07-26
Search bar closes itself after a few seconds 7 2021-12-27 2022-09-02
成功运行过工具箱,后来因为自己训练了一次模型就再也打不开工具箱了是什么情况? 3 2022-01-05 2022-08-22
with-let hides the original exception if it caused another one down the line 2 2021-01-30 2022-09-10
prelude/store.dhall-lang.org isn't updating 1 2021-10-14 2022-09-21
https://thegolden7.com/ 1 2022-09-12 2022-09-11
Unclear documentation regarding timezone parameters 2 2021-09-24 2022-08-23
Email template variable: __SHIPPING_METHOD__ needed 1 2022-01-19 2022-09-16
Bypass device authorization flow, for real 0 2021-09-30 2022-09-13
Mozilla VPN app for Windows connects twice (double-tone) when connecting using Single-Hop 2 2022-06-20 2022-08-11
WebRTC: 推RTC拉RTMP,VLC首屏很久2分钟左右 1 2022-07-05 2022-09-17
[BUG][aspnetcore] Resolve Discrepancy between build.bat/sh files and launchProfiles 1 2022-04-23 2022-09-14
Vertical spacer behavior has changed on mobile 7 2021-05-10 2022-08-14
New assist: add enum variant 4 2022-03-06 2022-08-20
Is that any way to get event of new member joined to the channel? 15 2017-12-07 2022-09-24
Service Map container showing error 1 2022-05-18 2022-09-17
Automated testing using GitHub Actions 0 2022-02-24 2022-09-07
[FEATURE] Use local maven repo for tests 0 2021-06-25 2022-08-16
Cannot select "Every day" in frequency popup 5 2021-11-06 2022-09-11
Ensure namespace manager reload context is not leaked 1 2021-07-05 2022-08-28
unknown or unsupported field - consul and tcp 3 2022-05-09 2022-09-27
Email address 6 2019-03-19 2022-01-10
Issues with dependencies 9 2021-05-29 2022-09-04
[Workflow] Command workflow:dump not working 4 2021-11-05 2022-07-13
[CP] Remove context assertion from Android platform views using Virtual Display 5 2022-09-09 2022-09-26
`Theme.of(context).accentColor` not being migrated by `dart fix` 8 2021-09-09 2022-08-14